1. Field of the Invention
The present invention relates to a stacked memory having a plurality of stacked memory chips, and more particularly to a memory arrangement, a bank arrangement, and a refresh control of a stacked memory.
2. Description of the Related Art
Recently, electronic equipment has been miniaturized, and semiconductor devices used in electronic equipment also have been miniaturized. For example, small-sized electronic equipment such as cellular phones employs a three-dimensional stacked semiconductor device. The three-dimensional stacked semiconductor device has a plurality of stacked semiconductor chips, each of which is subjected to wire bonding so as to be housed in a single package. Thus, in order to achieve miniaturization of a semiconductor device, semiconductor chips are stacked so as to form a three-dimensional stacked semiconductor device.
In order to achieve further miniaturization and high-speed operation, there has recently been developed a stacked semiconductor device using through electrodes instead of wire bonding. In such a stacked semiconductor device, stacked semiconductor chips are connected to each other by through electrodes, which extend through the semiconductor chips. The use of through electrodes reduces a space and an inductor which would be caused by wire bonding, and allows a semiconductor device to achieve further miniaturization and high-speed operation.
A stacked memory with a plurality of stacked memory chips has been developed as one of such stacked semiconductor devices. A stacked memory can be substituted for a memory module by stacking a plurality of semiconductor chips. For example, such a stacked memory includes a stacked dynamic random access memory (DRAM) having stacked DRAM chips which are formed on memory core layers. When a stacked memory is substituted for a currently used memory or memory module, the stacked memory should be arranged so as to match specifications of the currently used memory or memory module. For example, design of memory core layers should be changed for parity operation and for no-parity operation. Specifically, x16-bit products should be changed into x18-bit products when the parity operation is executed. Further, it is to be noted that each of the DRAM chips tends to be divided into a plurality of banks. Under the circumstances, if the DRAM chips are simply stacked one upon another, the number of banks widely varies depending on the number of stacks. This requires preparation of a great number of DRAM specifications for every one of the bank numbers. Furthermore, any refresh control methods corresponding to a stacked structure have not been established yet.
With regard to a stacked semiconductor device having stacked semiconductor chips, the following references are known as the prior art. Japanese laid-open patent publication No. 9-265774 (Patent Document 1) discloses an interleave control performed between stacked memory chips in order to shorten access time. Japanese laid-open patent publication No. 2004-327474 (Patent Document 2) discloses a stacked memory that stacks an IO chip and a plurality of DRAM chips together. With this structure, the IO chip converts system data signals and internal data in the DRAM chips and controls the stacked memory.
Patent Document 1 discloses an improvement of an access method of a stacked memory but is silent on a bank arrangement or a refresh method of DRAM chips. According to Patent Document 2, it is assumed that each of the DRAM chips has a single bank arrangement. Accordingly, no problems arise with regard to a plural bank arrangement of the DRAM chips. Further, Patent Document 2 is silent on a refresh method of the DRAM chips. Thus, Patent Documents 1 and 2 do not recognize the aforementioned problems to be resolved by the present invention. Patent Documents 1 and 2 are silent on an arrangement of a stacked memory or an address assignment, and fail to teach or suggest any technology to resolve the aforementioned problems.
In addition, a stacked memory should also have a structure matched with specifications of the currently used memory or memory module. However, no methods have been established yet so as to be matched with such demands. Accordingly, an arrangement of semiconductor chips should be changed for parity operation and for no-parity operation. Specifically, x16-bit products for no-parity operation should be changed into x18-bit products for parity operation. Further, if stacking is simply conducted, the bank numbers should change according to the number of stacks, as mentioned before. Such a change of the bank numbers needs to change DRAM specifications for the bank numbers. Furthermnore, no optimal refresh control methods corresponding to a stacked structure have been established yet.